In the next generation of integrated circuit manufacturing processes, gate electrodes of a complementary metal oxide semiconductor (CMOS) device generally use high-k metal gate technology. Generally speaking, for advanced CMOS technology nodes, there are two different processes for forming high-K metal gate. One process is to firstly form a high-K dielectric layer followed by a metal gate, and another process is after the high-K dielectric layer followed by the metal gate. The first process includes forming a dummy gate structure on a semiconductor substrate. The dummy gate structure includes from bottom to top a bottom-interface layer, a high-K dielectric layer overlying the bottom interface layer, a capping layer over the high-K dielectric layer, and a sacrificial layer over the capping layer. The first process also includes forming sidewall structures on opposite sides of the dummy gate structure, removing the sacrificial layer to form a groove between the sidewall structures, and sequentially depositing in the groove a work function metal layer, a barrier layer and a wetting layer. The first process further includes filling the groove with a metal material (generally aluminum). The second process includes forming a dummy gate structure on a semiconductor substrate. The dummy gate structure includes from bottom to top a sacrificial dielectric layer and a sacrificial gate layer. The second process also includes forming sidewall structures on opposite sides of the dummy gate structure, removing the sacrificial layer to form a trench between the sidewall structures, and sequentially depositing in the trench an interface layer, a high-K dielectric layer, a capping layer, a work function metal layer, a barrier layer, a wetting layer, and filling the groove with a metal material (which is generally aluminum).
There are generally two ways of removing the sacrificial gate layer in the high-K metal gate process. The first way includes concurrently removing the sacrificial layer of the dummy gate structure in the NMOS and PMOS regions. For example, as shown in FIG. 1A, an isolation structure 101 separates a semiconductor substrate 100 into a NMOS region and a PMOS region. A dummy gate structure 102 is separately formed on the NMOS and PMOS regions. Dummy gate structure 102 includes from bottom to top a high-K dielectric layer 102a and a sacrificial gate layer 102b. Sidewall structures 103 are formed on opposite sides of dummy gate structures 102. A contact hole etch stop layer 104 and an interlayer dielectric layer 2105 are sequentially formed on semiconductor substrate 100. A chemical mechanical polishing (CMP) process is performed to expose a top surface of dummy gate structure 102. Thereafter, as shown in FIG. 1B, sacrificial gate layer 102b in the NMOS and PMOS regions is concurrently removed. A suitable work function metal layer 106 is deposited on the PMOS region covering interlayer dielectric layer 105, sidewall structures 103, and high-K dielectric layer 102a. Thereafter, as shown in FIG. 1C, a portion of work function metal layer 106 is removed by etching from the NMOS region, and a suitable work function metal layer 107 is deposited covering interlayer dielectric layer 105, sidewall structures 103 and high-K dielectric layer 102a of the NMOS region and work function metal layer 106 of the PMOS region. Thereafter, as shown in FIG. 1D, a metal barrier layer 108 and a metal gate material layer 109 are sequentially deposited to cover work function metal layer 107. A chemical mechanical polishing is performed to expose interlayer dielectric layer 105 to complete the formation of the high-K metal gate. This approach is disadvantageous due to the suitable work function metal layer 107 of the NMOS region is also formed in the high-K metal gate of the PMOS region, therefore, the work function metal layer of the high-K metal gate disposed in the NMOS and PMOS regions cannot be individually adjusted.
A second approach is to individually remove the sacrificial layer in the dummy gate structures of the NMOS and PMOS regions. For example, as shown in FIG. 2A, an isolation structure 201 separates a semiconductor substrate 200 into a NMOS region and a PMOS region. Dummy gate structure 202 is formed in the NMOS and PMOS regions. Dummy gate structure 202 includes from bottom to top a high-K dielectric layer 202a and a sacrificial layer 202b. Sidewall structures 203 are formed on opposite sides of dummy gate structure 202. Contact hole etch stop layer 204 and an interlayer dielectric layer 205 are sequentially formed, and a chemical mechanical polishing is then performed to expose a top surface of dummy gate structure 202. Thereafter, as shown in FIG. 2B, a patterned photoresist layer 206 is formed covering the NMOS region, sacrificial layer 202b of dummy gate structure in the PMOS region is removed by etching using the patterned photoresist layer 206 as a mask. Thereafter, as shown in FIG. 2C, the patterned photoresist layer 206 is removed, a work function metal layer 207a, a barrier layer 207b, and a metal gate layer 207c are sequentially deposited. A CMP is performed to expose interlayer dielectric layer 205 to complete the formation of a high-K metal gate 207. Thereafter, as shown in FIG. 2D, a second patterned photoresist layer is formed covering the PMOS region, and using the second patterned photoresist layer as a mask to remove the sacrificial layer 202b of dummy gate structure 202 in the NMOS region. Thereafter, the second patterned photoresist layer is removed, a work function metal layer 208a, a barrier layer 208b, and a metal gate layer 208c are sequentially deposited. A CMP is performed to expose interlayer dielectric layer 205 to complete the formation of a high-K metal gate 208. This approach is disadvantageous due to the fact that two patterned photoresist layers are needed to separately cover the NMOS and PMOS regions, thereby increasing the production costs. Furthermore, etch residues generated by two etchings may greatly affect the subsequent depositions of the work function metal layer, the barrier layer, and the metal gate layer.
Thus, the need exists for solutions to the problems with the prior art.